This invention relates generally to digital computer systems and more specifically to memory testing apparatus.
Many present day computers are designed to be modular in nature to provide the capability to increase or decrease the capacity of the computer by the addition or deletion of modules of the appropriate type. The memory capacity of the modular computer may be increased or decreased through the addition or deletion of one or more memory modules which normally operate asynchronously with respect to each other and with respect to other modules within the modular computer. The memory array of a memory module is the actual storage element of the memory module. Whereas memory arrays have been fabricated using many technologies in the past, semiconductor technologies currently have widespread popularity. To make semiconductor memory arrays economically feasible requires large densities. Monolithic devices of 2.sup.14, 2.sup.15 and even 2.sup.16 bit positions are now possible. Two disadavantages of such large densities on a single monolithic device are increased failure probability and increased device replacement cost. The common technique for addressing the problems is the use of error correction circuitry (ECC). The designer merely assumes the existence of errors in a memory array and designs ECC into the memory module to correct the assumed errors.
A major problem in the use of ECC is the testability of the ECC and supporting circuitry. The ECC may be effectively tested using special purpose test equipment, but this approach is usually too costly for other than the in-factory testing. A common method of field testing utilizes test software which reads and writes test patterns into the memory array and thereby inferentially tests the ECC. This technique is widely used despite the time consuming nature of the software testing. The greatest disadvantage of this technique is the necessary reliance upon assuming correct operation of the memory array. This assumption may be so unrealistic (i.e., probability of memory array failure may be so high) as to render the testing technique unacceptably unreliable. The present invention permits the cost advantages of software testing of ECC without reliance upon the use of the memory array in the testing process.